Electronic devices comprising silicon carbide materials

ABSTRACT

An electronic device comprising a stack structure comprising one or more stacks of materials and one or more silicon carbide materials adjacent to the one or more stacks of materials. The materials of the one or more stacks comprise a single chalcogenide material and one or more of a conductive carbon material, a conductive material, and a hardmask material. The one or more silicon carbide materials comprises silicon carbide, silicon carboxide, silicon carbonitride, silicon carboxynitride, and also comprise silicon-carbon covalent bonds. The one or more silicon carbide materials is configured as a liner or as a seal. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.

TECHNICAL FIELD

Embodiments disclosed herein relate to electronic devices and electronicdevice fabrication. More particularly, embodiments of the disclosurerelate to electronic devices comprising one or more silicon carbidematerials and to related methods and systems.

BACKGROUND

Electronic device (e.g., semiconductor device, memory device) designersoften desire to increase the level of integration or density of features(e.g., components) within an electronic device by reducing thedimensions of the individual features and by reducing the separationdistance between neighboring features. Electronic device designers alsodesire to design architectures that are not only compact, but offerperformance advantages, as well as simplified designs. Reducing thedimensions and spacing of features has placed increasing demands on themethods used to form the electronic devices. One solution has been toform three-dimensional (3D) electronic devices, such as 3D cross-pointmemory devices, in which the features are arranged vertically ratherthan horizontally. To form the features, multiple materials arepositioned over one another and are etched to form stacks of thematerials. The materials of the stacks include chalcogenide materialsand electrode materials. Some of the materials of the stacks aresensitive to subsequently conducted process acts, such as to processtemperatures or etch conditions of the subsequent process acts. Thematerials of the stacks may, for example, be thermally sensitive orsensitive to etch chemistries and other process conditions.

To protect the materials of the stacks during formation of theelectronic device, a liner is formed over the stacks. In conventionalelectronic devices, the liner includes a layer of silicon nitride (SiN)and a layer of silicon oxide (SiO_(x)). However, the liner may notprovide sufficient protection when aggressive etch chemistries are usedto form the electronic device. In addition, process conditions used toform the silicon oxide on the silicon nitride may damage the siliconnitride of the liner. The layer of silicon oxide is formed on the layerof silicon nitride by an oxygen plasma-based process, such as a PEALDprocess, which damages (e.g., oxidizes) the layer of silicon nitride.

To further protect the materials of the stacks, a seal may be formedover the stacks, such as over the liner of the stacks. In conventionalelectronic devices, the seal includes silicon nitride in combinationwith silicon oxide. However, the seal may not uniformly cover sidewallsof the liner to sufficiently protect the materials of the stacks.

As aspect ratios of features continue to increase and the spacingbetween adjacent stacks continues to decrease with increasing memorydensity, the materials of the liner and/or of the seal may form abottleneck or pinch off, causing a so-called “bread loafing” effectbetween upper portions of the adjacent stacks. If, however, thematerials of the liner and/or of the seal are formed at a lowerthickness, the liner and/or of the seal may not provide the desiredprotective properties. When a dielectric material is subsequently formedbetween the adjacent stacks, any bottlenecked portion of the linerand/or of the seal prevents the dielectric material from completelyfilling openings between the stacks and forms voids in the dielectricmaterial.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-4 are cross-sectional views of stack structures including aliner containing a silicon carbide material at various stages of formingthe stack structures according to embodiments of the disclosure;

FIGS. 5-7 are cross-sectional views of stack structures including aliner containing a silicon carbide material and a seal including asilicon carbide material at various stages of forming the stackstructures according to embodiments of the disclosure;

FIG. 8 is a perspective view of an array of memory cells including stackstructures according to embodiments of the disclosure;

FIG. 9 is a functional block diagram of an electronic device includingstack structures according to embodiments of the disclosure;

FIG. 10 is a simplified block diagram of a system including stackstructures according to embodiments of the disclosure;

FIG. 11 is a graph showing carbon content of silicon carbide materialsaccording to embodiments of the disclosure as a function ofsilicon-carbon precursor:O₂ ratio;

FIG. 12 is a graph showing oxygen content of silicon carbide materialsaccording to embodiments of the disclosure as a function ofsilicon-carbon precursor:O₂ ratio;

FIGS. 13A-13D are graphs showing wet etch rates of silicon carbidematerials according to embodiments of the disclosure using 200:1 HF(FIGS. 13A and 13B), 100:1 HF (FIG. 13C), and 10:1 HF (FIG. 13D); and

FIGS. 14 and 15 are graphs showing chalcogenide loss for silicon carbidematerials according to embodiments of the disclosure.

DETAILED DESCRIPTION

An electronic device (e.g., an apparatus, a semiconductor device, amemory device) that includes a liner adjacent to (e.g., over) one ormore stacks of materials is disclosed. The liner includes a materialcontaining silicon atoms and carbon atoms (e.g., a silicon carbidematerial). The stacks include one or more thermally sensitive materialsand/or one or more oxidation sensitive materials, and the siliconcarbide material of the liner is formed over the materials of the stacksto protect the sensitive materials during subsequent process acts. Thesilicon carbide material of the liner is conformally formed over thestacks using a low temperature, non-oxidative process that does notsubstantially affect (e.g., damage) the materials of the stacks or otherexposed materials of the electronic device. A seal containing the sameor a different silicon carbide material may, optionally, be formed overthe liner containing the silicon carbide material. The silicon carbidematerial of the liner and/or of the seal is formed by a radical chemicalvapor deposition (CVD) process using a silicon-carbon precursor. Afterformation, the amount of carbon in the silicon carbide material may betailored (e.g., tuned) depending on desired properties (e.g., etch rate,etch resistance, degree of conformality, etc.) of the silicon carbidematerial of the liner and/or of the seal. By conducting a treatment acton the silicon carbide material as initially formed, the carbon contentof the silicon carbide material in the electronic device may be tailoredto provide the desired properties.

The following description provides specific details, such as materialtypes, material thicknesses, and process conditions in order to providea thorough description of embodiments described herein. However, aperson of ordinary skill in the art will understand that the embodimentsdisclosed herein may be practiced without employing these specificdetails. Indeed, the embodiments may be practiced in conjunction withconventional fabrication techniques employed in the semiconductorindustry. In addition, the description provided herein does not form acomplete description of an electronic device or a complete process flowfor manufacturing the electronic device and the structures describedbelow do not form a complete electronic device. Only those process actsand structures necessary to understand the embodiments described hereinare described in detail below. Additional acts to form a completeelectronic device may be performed by conventional techniques.

Unless otherwise indicated, the materials described herein may be formedby conventional techniques including, but not limited to, spin coating,blanket coating, chemical vapor deposition (CVD), atomic layerdeposition (ALD), plasma enhanced ALD, physical vapor deposition (PVD)(including sputtering, evaporation, ionized PVD, and/or plasma-enhancedCVD), or epitaxial growth. Alternatively, the materials may be grown insitu. Depending on the specific material to be formed, the technique fordepositing or growing the material may be selected by a person ofordinary skill in the art. The removal of materials may be accomplishedby any suitable technique including, but not limited to, etching (e.g.,dry etching, wet etching, vapor etching), ion milling, abrasiveplanarization (e.g., chemical-mechanical planarization), or other knownmethods unless the context indicates otherwise.

Drawings presented herein are for illustrative purposes only, and arenot meant to be actual views of any particular material, component,structure, electronic device, or electronic system. Variations from theshapes depicted in the drawings as a result, for example, ofmanufacturing techniques and/or tolerances, are to be expected. Thus,embodiments described herein are not to be construed as being limited tothe particular shapes or regions as illustrated, but include deviationsin shapes that result, for example, from manufacturing. For example, aregion illustrated or described as box-shaped may have rough and/ornonlinear features, and a region illustrated or described as round mayinclude some rough and/or linear features. Moreover, sharp angles thatare illustrated may be rounded, and vice versa. Thus, the regionsillustrated in the figures are schematic in nature, and their shapes arenot intended to illustrate the precise shape of a region and do notlimit the scope of the present claims. The drawings are not necessarilyto scale. Additionally, elements common between figures may retain thesame numerical designation.

As used herein, the singular forms “a,” “an,” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise.

As used herein, “and/or” includes any and all combinations of one ormore of the associated listed items.

As used herein, “about” or “approximately” in reference to a numericalvalue for a particular parameter is inclusive of the numerical value anda degree of variance from the numerical value that one of ordinary skillin the art would understand is within acceptable tolerances for theparticular parameter. For example, “about” or “approximately” inreference to a numerical value may include additional numerical valueswithin a range of from 90.0 percent to 110.0 percent of the numericalvalue, such as within a range of from 95.0 percent to 105.0 percent ofthe numerical value, within a range of from 97.5 percent to 102.5percent of the numerical value, within a range of from 99.0 percent to101.0 percent of the numerical value, within a range of from 99.5percent to 100.5 percent of the numerical value, or within a range offrom 99.9 percent to 100.1 percent of the numerical value.

As used herein, spatially relative terms, such as “beneath,” “below,”“lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,”“right,” and the like, may be used for ease of description to describeone element's or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. Unless otherwise specified,the spatially relative terms are intended to encompass differentorientations of the materials in addition to the orientation depicted inthe figures. For example, if materials in the figures are inverted,elements described as “below” or “beneath” or “under” or “on bottom of”other elements or features would then be oriented “above” or “on top of”the other elements or features. Thus, the term “below” can encompassboth an orientation of above and below, depending on the context inwhich the term is used, which will be evident to one of ordinary skillin the art. The materials may be otherwise oriented (e.g., rotated 90degrees, inverted, flipped) and the spatially relative descriptors usedherein interpreted accordingly.

As used herein, the term “configured” refers to a size, shape, materialcomposition, and arrangement of one or more of at least one structureand at least one apparatus facilitating operation of one or more of thestructure and the apparatus in a pre-determined way.

As used herein, the term “electronic device” includes, withoutlimitation, a memory device, as well as semiconductor devices which mayor may not incorporate memory, such as a logic device, a processordevice, or a radiofrequency (RF) device. Further, an electronic devicemay incorporate memory in addition to other functions such as, forexample, a so-called “system on a chip” (SoC) including a processor andmemory, or an electronic device including logic and memory. Theelectronic device may be a 3D electronic device, such as a 3D crosspointmemory device, that includes sensitive materials.

As used herein, the term “liner material” or “liner” means and includesa silicon carbide material formulated to exhibit etch selectivitybetween the silicon carbide material and other exposed materials whensubjected to the same etch conditions. The liner may include one or morematerials, such as the silicon carbide material and one or more othermaterials, positioned adjacent to one another and that are formulated toexhibit the desired etch selectivity properties. A thickness of theliner is less than a thickness of the seal.

As used herein, reference to an element as being “on” or “over” anotherelement means and includes the element being directly on top of,adjacent to (e.g., laterally adjacent to, vertically adjacent to),underneath, or in direct contact with the other element. It alsoincludes the element being indirectly on top of, adjacent to (e.g.,laterally adjacent to, vertically adjacent to), underneath, or near theother element, with other elements present therebetween. In contrast,when an element is referred to as being “directly on” or “directlyadjacent to” another element, no intervening elements are present.

As used herein, the term “seal material” or “seal” means and includes asilicon carbide material formulated to exhibit barrier properties, suchas reducing or substantially preventing water from passing through thematerial. The seal may include one or more materials, such as thesilicon carbide material and one or more other materials, positionedadjacent to one another and that are formulated to exhibit the desiredbarrier properties. The thickness of the seal is greater than thethickness of the liner.

As used herein, the term “silicon carbide material” means and includes amaterial including silicon atoms and carbon atoms. The silicon carbidematerial may optionally include one or more of oxygen atoms, nitrogenatoms, or boron atoms. The silicon carbide material may include, but isnot limited to, silicon carbide, silicon carboxide, siliconcarbonitride, silicon carboxynitride, or silicon boronitrocarbide. Thesilicon carbide material may be a stoichiometric compound or anon-stoichiometric compound. The terms “silicon carboxide” or “oxygendoped silicon carbide” are used to refer to the silicon carbide materialhaving a general chemical formula of SiCO_(x), the terms “siliconcarbonitride” or “nitrogen doped silicon carbide” are used to refer tothe silicon carbide material having a general chemical formula ofSiCN_(y), and the terms “silicon carboxynitride” or “oxygen and nitrogendoped silicon carbide” are used to refer to the silicon carbide materialhaving a general chemical formula of SiCO_(x)N_(y). The term “siliconcarbide material” is used to collectively refer to one or more ofsilicon carbide, the silicon carbonitride, the silicon carboxide, or thesilicon carboxynitride. Silicon oxide (SiO_(x)) including only siliconatoms and oxygen atoms is excluded from the definition of a siliconcarbide material.

As used herein, the term “selectively etchable” means and includes amaterial that exhibits a greater etch rate responsive to exposure to agiven etch chemistry and/or process conditions relative to anothermaterial exposed to the same etch chemistry and/or process conditions.For example, the material may exhibit an etch rate that is at leastabout five times greater than the etch rate of another material, such asan etch rate of about ten times greater, about twenty times greater, orabout forty times greater than the etch rate of the another material.Etch chemistries and etch conditions for selectively etching a desiredmaterial may be selected by a person of ordinary skill in the art.

As used herein, the term “stack” means and includes a feature havingmultiple materials positioned vertically adjacent to one another. Atleast one of the materials of the stack may be sensitive to heat and/orto water. The materials of the stacks may include one or more conductive(e.g., electrically conductive) material, one or more chalcogenidematerial, and a hardmask material, or a combination thereof.

As used herein, the term “substantially” in reference to a givenparameter, property, or condition means and includes to a degree thatone of ordinary skill in the art would understand that the givenparameter, property, or condition is met with a degree of variance, suchas within acceptable manufacturing tolerances. By way of example,depending on the particular parameter, property, or condition that issubstantially met, the parameter, property, or condition may be at least90.0% met, at least 95.0% met, at least 99.0% met, or even at least99.9% met.

As used herein, the term “substrate” means and includes a material(e.g., a base material) or construction upon which additional materialsare formed. The substrate may be a an electronic substrate, asemiconductor substrate, a base semiconductor layer on a supportingstructure, an electrode, an electronic substrate having one or morematerials, layers, structures, or regions formed thereon, or asemiconductor substrate having one or more materials, layers,structures, or regions formed thereon. The materials on the electronicsubstrate or semiconductor substrate may include, but are not limitedto, semiconductive materials, insulating materials, conductivematerials, etc. The substrate may be a conventional silicon substrate orother bulk substrate comprising a layer of semiconductive material. Asused herein, the term “bulk substrate” means and includes not onlysilicon wafers, but also silicon-on-insulator (“SOI”) substrates, suchas silicon-on-sapphire (“SOS”) substrates and silicon-on-glass (“SOG”)substrates, epitaxial layers of silicon on a base semiconductorfoundation, and other semiconductor or optoelectronic materials, such assilicon-germanium, germanium, gallium arsenide, gallium nitride, andindium phosphide. The substrate may be doped or undoped.

As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and“lateral” are in reference to a major plane of a structure and are notnecessarily defined by Earth's gravitational field. A “horizontal” or“lateral” direction is a direction that is substantially parallel to themajor plane of the structure, while a “vertical” or “longitudinal”direction is a direction that is substantially perpendicular to themajor plane of the structure. The major plane of the structure isdefined by a surface of the structure having a relatively large areacompared to other surfaces of the structure.

Stack structures 100 including stacks 105, liner 110 adjacent to (e.g.,vertically adjacent to, over) the stacks 105, and openings 115 are shownin FIGS. 1 and 2. The liner 110 may include one or more liner portions,such as liner portions 110A, 110B. The stack structure 100 is formedadjacent to (e.g., vertically adjacent to, over) a substrate 120. Thestacks 105 are separated from one another by the openings 115, andadjacent stacks 105 are separated from one another by a distance D1. Thedistance D1 may depend on a pitch at which the stacks 105 of the stackstructure 100 are formed, which is selected depending on the intendeduse of the stack structure 100 in an electronic device containing thestack structure 100. Each stack 105 includes multiple materials, such asone or more conductive materials, one or more chalcogenide materials,and a hardmask material. As described in more detail below, the stackstructure 100 may be present in memory cells of the electronic device.

FIGS. 1 and 2 show the stacks 105 as including four materials 105A-105Dand conductive material 105E. However, the number of materials in thestacks 105 may be more than or less than five. One or more of thematerials of the stacks 105 may be heat sensitive or sensitive tooxidation. The stacks 105 may, for instance, include the conductivematerial 105E, one or more chalcogenide materials, one or moreconductive carbon materials, one or more conductive materials inaddition to the conductive material 105E, and the hardmask material. Byway of example only, the stacks 105 may include the conductive material105E over the substrate 120, a first conductive carbon material over theconductive material 105E, one or more chalcogenide materials over thefirst conductive carbon material, a second conductive carbon materialover the one or more chalcogenide materials, and the hardmask materialover the second conductive carbon material. The stacks 105 may, forexample, include one or more chalcogenide materials and one or moreconductive carbon materials, which are sensitive to heat or to oxidation(e.g., oxidative conditions), to which conditions the materials may beexposed during and following the formation of the stacks 105 or duringformation of the liner 110 or a seal 125 (see FIG. 5). In someembodiments, the stacks 105 include the conductive material 105E overthe substrate 120, the first conductive carbon material over theconductive material 105E, a chalcogenide material over the firstconductive carbon material, a second conductive carbon material over thechalcogenide material, and the hardmask material over the secondconductive carbon material. In other embodiments, the stacks 105 includethe conductive material 105E over the substrate 120, the firstconductive carbon material over the conductive material 105E, a firstchalcogenide material over the first conductive carbon material, asecond chalcogenide material over the first chalcogenide material, asecond conductive carbon material over the second chalcogenide material,and the hardmask material over the second conductive carbon material.

The conductive material 105E of the stacks 105 may include anelectrically conductive material including, but not limited to,tungsten, aluminum, copper, titanium, tantalum, platinum, alloysthereof, heavily doped semiconductor material, polysilicon, a conductivesilicide, a conductive nitride, a conductive carbon, a conductivecarbide, or combinations thereof. The conductive material 105E may, forexample, be configured as an access line, a word line, a contact, adigit line, a bit line, etc. In some such embodiments, the conductivematerial 105E is tungsten. The conductive material 105E mayalternatively be configured as an electrode. In some such embodiments,the conductive material 105E is conductive carbon.

The conductive carbon materials of the stacks 105 may include, but arenot limited to, an electrically conductive carbon material.

The chalcogenide material of the stacks 105 may be a chalcogenide glass,a chalcogenide-metal ion glass, or other chalcogenide-containingmaterial. The chalcogenide material may be a binary or multinary(ternary, quaternary, etc.) compound including at least one chalcogenideatom and at least one more electropositive element. As used herein, theterm “chalcogenide” means and includes an element of Group VI of thePeriodic Table, such as oxygen (O), sulfur (S), selenium (Se), ortellurium (Te). The electropositive element may include, but is notnecessarily limited to, nitrogen (N), silicon (Si), nickel (Ni), gallium(Ga), germanium (Ge), arsenic (As), silver (Ag), indium (In), tin (Sn),antimony (Sb), gold (Au), lead (Pb), bismuth (Bi), or combinationsthereof. By way of example only, the chalcogenide material may include acompound including Ge, Sb, and Te (i.e., a GST compound), such asGe₂Sb₂Te₅, however, the disclosure is not so limited and thechalcogenide material may include other compounds including at least onechalcogenide element. The chalcogenide material may be doped or undopedand may have metal ions mixed therein. By way of example only, thechalcogenide material may be an alloy including indium, selenium,tellurium, antimony, arsenic, bismuth, germanium, oxygen, tin, orcombinations thereof. In some embodiments, the stack 105 includes one(e.g., a single) chalcogenide material. In other embodiments, the stack105 includes two chalcogenide materials. The two chalcogenide materialsmay be adjacent to one another or may be spaced apart by one or more ofthe other materials of the stacks 105.

The hardmask material of the stacks 105 may exhibit a different etchselectivity relative to other materials in the stacks 105 and relativeto one or more other conductive materials formed on the stacks 105during subsequent process acts. The hardmask material may include, butis not limited to, silicon nitride or amorphous carbon. The hardmaskmaterial may optionally be removed before conducting subsequent processacts. In some embodiments, the hardmask material is silicon nitride.

The materials of the stacks 105 are positioned adjacent to (e.g.,vertically adjacent to) one another. The materials of the stacks 105 maybe formed vertically adjacent to one another by conventional techniquesand the materials patterned to form the stacks 105 separated from oneanother by the openings 115. The materials may be patterned (e.g., aportion of the materials removed) by conventional techniques, such as byetching the materials using conventional photolithography and etchingtechniques. The materials may, for example, be exposed to an anisotropicetch process, such as a dry plasma etch process or a reactive ion etchprocess, to form the stacks 105. Conventional etch chemistries and etchconditions may be used to form the stacks 105 and the openings 115. Theresulting stacks 105 may be high aspect ratio (HAR) features having anaspect ratio (i.e., a ratio of width to depth) of greater than or equalto about 5:1, such as from about 5:1 to about 100:1, from about 5:1 toabout 50:1, from about 10:1 to about 40:1, from about 10:1 to about30:1, from about 10:1 to about 20:1, from about 20:1 to about 50:1, fromabout 20:1 to about 40:1, or from about 20:1 to about 30:1. The openings115 may also exhibit a high aspect ratio. The stacks 105 may be formedat a half pitch of from about 3 nm to about 100 nm, such as from about10 nm to about 30 nm, from about 15 nm to about 25 nm or from about fromabout 15 nm to about 20 nm. In some embodiments, the stacks 105 areformed at a half pitch of 20 nm. In other embodiments, the stacks 105are formed at a half pitch of 14 nm. In addition to the stacks 105 beingconfigured as lines, other geometries, such as pillars, may be used. Theconductive material 105E of the stacks 105 may be patterned at the sametime as the other materials of the stacks 105 or may be patterned afterpatterning the materials 105A-105D, as shown in FIG. 3.

The liner 110A, 110B may be formed adjacent to (e.g., over) the stacks105, as shown in FIG. 2. While the drawings illustrate the liner 110 asincluding two liner portions 110A, 110B, the liner 110 may include asingle liner portion 110B or may include three or more portionsdepending on the degree of protection to be achieved. The liner 110A,110B is conformally formed on sidewalls of the materials 105A-105D ofthe stacks 105 at a thickness sufficient to protect the materials105A-105D of the stacks 105 during process acts conducted during orafter the formation of the stacks 105 or before or after the optionalseal 125 (see FIG. 5) is formed adjacent to (e.g., over) the liner 110A,110B. The subsequent process acts may include, but are not limited to,an etch process (e.g., a dry etch process, a wet etch process) or aplasma-based process, such as a treatment process or a densificationprocess. The liner 110A, 110B may also protect the materials of thestacks 105 during process acts conducted to clean the stacks 105. Theliner 110A, 110B is also formed on horizontal surfaces of the conductivematerial 105E to protect the conductive material 105E.

As shown in FIG. 2, adjacent stacks 105 of the stack structure 100 areseparated from one another by a distance D2 that is less than thedistance D1. The distance D2 may range from about 3 nm to about 300 nm,such as from about 20 nm to about 60 nm, from about 20 nm to about 40nm, or from about 40 nm to about 60 nm depending on a pitch at which thestacks 105 of the stack structure 100 are formed and a thickness of theliner 110A, 110B. The distance D2 between adjacent stacks 105 may beequal to the thickness D1 minus two times the thickness of the liner110, 110B.

The liner 110A is formed of a dielectric material, such as siliconnitride (SiN). The liner 110A may be conformally formed over the stacks105 by conventional techniques, such as by PECVD. The liner 110A mayprovide adhesion properties or protective properties to the liner 110.The liner portion 110A has a thickness from about 10 Å to about 60 Å.The liner 110B may be conformally formed over the liner 110A, such asforming the liner 110B directly over (e.g., in contact with) the liner110A. Alternatively, the liner 110 may include only the silicon carbidematerial of the liner portion 110B, where the silicon carbide materialof the liner 110B is directly over (e.g., in contact with) the stacks105. For instance, as the spacing between adjacent stacks 105 of thestack structure 100 decreases, the silicon carbide material may beformed directly on the stacks 105 such that only the liner 110B ispresent.

The liner 110B may be formed of the silicon carbide material. The liner110B is formed by a radical CVD process that utilizes one (e.g., asingle) silicon-carbon precursor that includes covalent bonds betweensilicon atoms and carbon atoms of the silicon-carbon precursor. Theresulting silicon carbide material, therefore, includes covalent bondsbetween the silicon atoms and the carbon atoms and is more stable (e.g.,thermodynamically stable) than conventional silicon carbide materialsformed by other processes. The silicon carbide material of the liner110B, as initially formed, may include between about 2 atomic percent(at. %) and about 50 at. % carbon, such as between about 2 at. % andabout 40 at. % carbon, between about 2 at. % and about 30 at. % carbon,between about 5 at. % and about 50 at. % carbon, between about 5 at. %and about 40 at. % carbon, between about 5 at. % and about 30 at. %carbon, between about between about 10 at. % and about 50 at. % carbon,between about 15 at. % and about 50 at. % carbon, between about 20 at. %and about 50 at. % carbon, between about 25 at. % and about 50 at. %carbon, between about 30 at. % and about 50 at. % carbon, between about35 at. % and about 50 at. % carbon, between about 40 at. % and about 50at. % carbon, between about 45 at. % to about 50 at. % carbon, betweenabout 10 at. % and about 30 at. % carbon, between about 15 at. % andabout 30 at. % carbon, between about 20 at. % and about 30 at. % carbon,between about 25 at. % and about 30 at. % carbon, between about 30 at. %and about 50 at. % carbon, between about 35 at. % and about 50 at. %carbon, between about 40 at. % and about 50 at. % carbon, between about35 at. % and about 45 at. % carbon, or between about 10 at. % and about25 at. % carbon. The radical CVD process may be a non-oxidative processthat does not affect (e.g., damage) the liner 110B. The silicon carbidematerial of the liner 110B may exhibit a high degree of conformality andexhibit a high resistance to etch chemistries used in subsequent processacts. The liner portion 110B has a thickness from about 10 Å to about 60Å.

To form the liner 110B, the stack structure 100 including the stacks 105and liner 110A may be placed into a reaction chamber and the siliconcarbide material of the liner 110B may be formed by the radical CVDprocess. The reaction chamber may be conventional equipment used in thesemiconductor industry. The silicon-carbon precursor, radical species,and optional carrier gas are introduced to the reaction chambercontaining the stack structure 100. The silicon-carbon precursor maycontain one or more silicon-carbon (Si—C) covalent bonds between thesilicon atoms and the carbon atoms of the silicon-carbon precursor. Thesilicon-carbon precursor may also contain one or more silicon-hydrogen(Si—H) covalent bonds and/or one or more silicon-silicon (Si—Si)covalent bonds. The silicon-carbon precursor may be a gas at atemperature at which the silicon carbide material of the liner 110B isformed. By using the silicon-carbon precursor including thesilicon-carbon covalent bonds, the silicon carbide material of the liner110B, which also includes silicon-carbon covalent bonds, may be formedat a low temperature and using less aggressive process conditions sinceforming Si—C covalent bonds is thermodynamically not favored. Thesilicon-carbon precursor may include between about 2 at. % and about 45at. % silicon, between about 2 at. % and about 50 at. % carbon, betweenabout 0 at. % and about 45 at. % oxygen, and between about 0 at. % andabout 45 at. % nitrogen.

Depending on a desired material composition of the silicon carbidematerial, the silicon-carbon precursor may optionally include covalentbonds between the silicon atoms and nitrogen atoms of the silicon-carbonprecursor or covalent bonds between the silicon atoms and oxygen atomsof the silicon-carbon precursor in addition to the covalent bondsbetween the silicon atoms and carbon atoms. If, for example, the siliconcarbide material includes oxygen, the silicon-carbon precursor mayinclude the one or more silicon-hydrogen (Si—H) covalent bonds, the oneor more Si—C covalent bonds, the one or more silicon-silicon (Si—Si)covalent bonds, and one or more silicon-oxygen (Si—O) covalent bonds.If, for example, the silicon carbide material includes nitrogen, thesilicon-carbon precursor may include the one or more silicon-hydrogen(Si—H) covalent bonds, the one or more Si—C covalent bonds, the one ormore silicon-silicon (Si—Si) covalent bonds, and one or moresilicon-nitrogen (Si—N) covalent bonds. If, for example, the siliconcarbide material includes oxygen and nitrogen, the silicon-carbonprecursor may include the one or more silicon-hydrogen (Si—H) covalentbonds, the one or more Si—C covalent bonds, the one or moresilicon-silicon (Si—Si) covalent bonds, one or more silicon-nitrogen(Si—N) covalent bonds, and one or more silicon-oxygen (Si—O) covalentbonds. The silicon-carbon precursor may be a linear siloxane, a cyclicsiloxane, a monosilane, an alkyl silane, an alkoxy silane, or asilazane. Alternatively, the silicon-carbon precursor may have a generalchemical formula of Si—R, where R is an alkyl group; Si—Ar, where Ar isan aryl group; or Si—OR or Si—OAr. Such silicon-carbon precursors areknown in the art and may be commercially available from numeroussources, such as from LAM Research Corp. (Fremont, Calif.). A singletype of silicon-carbon precursor may be used to form the silicon carbidematerial by appropriately selecting the silicon-carbon precursor tocontain the covalent bonds (e.g., Si—C covalent bonds, Si—Si covalentbonds, Si—O covalent bonds, Si—N covalent bonds) to be present in theresulting silicon carbide material. In other words, the Si—C covalentbonds, Si—Si covalent bonds, Si—O covalent bonds, Si—N covalent bondsare formed (e.g., present) in the silicon-carbon precursor beforeradical species are formed.

The radical species may, for example, include hydrogen radicals (H′),oxygen radical species, or nitrogen radical species. The hydrogenradicals may be generated by conventional techniques, such as subjectinghydrogen gas (H₂) to a plasma in a remote plasma source. The generationof the hydrogen radicals from the hydrogen gas is conventional and isnot described in detail herein. The plasma source may include, but isnot limited to, a capacitively coupled plasma (CCP), an inductivelycoupled plasma (ICP), a microwave (MW) plasma, a DC plasma, or alaser-created plasma. The hydrogen radicals are generated at a highpressure using a high powered, remote ICP source. When reacted with thesilicon-carbon precursor, the hydrogen radicals may be in a sufficientlylow energy state that the Si—C covalent bonds in the silicon-carbonprecursor do not react with (e.g., are not broken by) the hydrogenradicals during the formation of the silicon carbide material on thestacks 105. The hydrogen radicals may initially be in an excited energystate, which relaxes to low energy state hydrogen radicals (e.g., groundenergy state hydrogen radicals). The silicon carbon precursor and thehydrogen radicals may be sufficiently reactive with one another thatplasma conditions are not used to form the silicon carbide material ofthe liner 110B. The low energy state hydrogen radicals may react withthe silicon-carbon precursor to break Si—Si covalent bonds and/or Si—Hcovalent bonds, activating the silicon-carbon precursor and formingradicals of the silicon-carbon precursor. The activated silicon-carbonprecursor includes reactive sites and the hydrogen radicals initiatecrosslinking at the reactive sites of the silicon-carbon precursor suchthat molecules of the activated silicon-carbon precursor react with oneanother to form the silicon carbide material of the liner 110B. Radicalsof the activated silicon-carbon precursor may exhibit a low stickingcoefficient. Since an oxidation reaction environment is not used in theradical based reactions, the silicon carbide material is able to beformed by the radical CVD process with low residence time reactions andat a low temperature. Substantially all of the hydrogen radicals may bein the low energy state or in the ground state and may react with thesilicon-carbon precursor. By way of example only, greater than about 90%or greater than about 95% of the hydrogen radicals may be in the lowenergy state or the ground state. Therefore, the stack structure 100including the stacks 105 and liner 110A is exposed to a high density ofthe hydrogen radicals.

If the silicon-carbon precursor also includes Si—O covalent bonds, thehydrogen radicals may be in a sufficiently low energy state that theSi—C covalent bonds and the Si—O covalent bonds do not react with (e.g.,are not broken by) the hydrogen radicals during the formation of thesilicon carbide material. If the silicon-carbon precursor also includesSi—N covalent bonds, the hydrogen radicals may be in a sufficiently lowenergy state that the Si—C covalent bonds and the Si—N covalent bonds donot react with (e.g., are not broken by) the hydrogen radicals duringthe formation of the silicon carbide material. If the silicon-carbonprecursor also includes Si—O covalent bonds and Si—N covalent bonds, thehydrogen radicals may be in a sufficiently low energy state that theSi—C covalent bonds, the Si—O covalent bonds, and the Si—N covalentbonds do not react with (e.g., are not broken by) the hydrogen radicalsduring the formation of the silicon carbide material.

The low energy state hydrogen radicals react with the silicon-carbonprecursor to form the silicon carbide material on the stacks 105, suchas on the sidewalls of the materials of the stacks 105. The processconditions are selected such that the Si—Si covalent bonds and the Si—Hcovalent bonds in the silicon-carbon precursor are selectively brokenwhile the Si—C covalent bonds and the Si—O covalent bonds and/or theSi—N covalent bonds are not broken. The Si—C bonds in the silicon-carbonprecursor, and the Si—O covalent bonds and/or the Si—N covalent bonds ifpresent, are thermodynamically stable under the process conditions ofthe radical CVD process relative to the Si—Si covalent bonds and theSi—H covalent bonds in the silicon-carbon precursor. The silicon andcarbon of the silicon-carbon precursor contribute to substantially allof the silicon and carbon in the silicon carbide material as initiallyformed. If the silicon-carbon precursor includes one or more of oxygenand nitrogen, the silicon-carbon precursor contributes substantially allof the oxygen and nitrogen of the silicon carbide material as initiallyformed.

The process conditions of the radical CVD process substantially preservethe Si—C covalent bonds of the silicon-carbon precursor. In other words,the Si—C covalent bonds are present in the silicon carbide materialafter reacting the silicon-carbon precursor and the low energy statehydrogen radicals. If the silicon carbide material is a siliconcarboxide, the Si—C covalent bonds and the Si—O covalent bonds may bepresent in the silicon carbide material. If the silicon carbide materialis a silicon carbonitride, the Si—C covalent bonds and the Si—N covalentbonds may be present in the silicon carbide material. If the siliconcarbide material is a silicon carboxynitride, the Si—C covalent bonds,the Si—O covalent bonds, and the Si—N covalent bonds may be present inthe silicon carbide material. The reactive species and thesilicon-carbon precursor may be introduced into the reaction chamber ata sufficient flow rate, temperature, pressure, residence time, RF power,etc., to maintain the hydrogen radicals in the low energy state or theground state. By way of example only, the temperature of the stackstructure 100 within the reaction chamber may be from about 50° C. toabout 500° C., such as from about 50° C. to about 450° C. The pressurewithin the reaction chamber may be less than or equal to about 35 TOM

The silicon carbide material as formed may be a substantiallyhomogeneous chemical composition or may be a heterogeneous chemicalcomposition, such as including a gradient of carbon across a thicknessof the silicon carbide material. By way of example only, the siliconcarbide material may include a silicon-rich portion proximal to thestacks 105, with the carbon content of the silicon carbide materialincreasing distal to the stacks 105. Alternatively, the silicon carbidematerial may be a substantially homogenous composition across itsthickness. The liner 110B may exhibit a step coverage of greater than orequal to about 75%, greater than or equal to about 80%, greater than orequal to about 85%, greater than or equal to about 90%, greater than orequal to about 95%, or greater than or equal to about 99%.

Forming the silicon carbide material of the liner 110B by the radicalCVD process enables the silicon carbide material to be formed withoutusing a direct plasma, which reduces plasma damage to the stackstructure 100. Since the silicon-carbon precursor includes the desiredcovalent bonds, the silicon carbide material is able to be formed at alower temperature and using only a single silicon-carbon precursor.Since forming Si—C covalent bonds is not thermodynamically favored atthe process conditions of the radical CVD process, substantially thesame covalent bonds existing in the silicon-carbon precursor are presentin the silicon carbide material of the liner 110B. In addition, the lowsticking coefficient of the radicals enables the silicon carbidematerial to be formed at a high step coverage, such as at a stepcoverage of greater than or equal to about 85%.

The silicon carbide material according to embodiments of the disclosurediffers from a silicon carbide material formed using separate siliconprecursors and carbon precursors as the source of silicon and carbon,respectively. The silicon carbide material formed by the radical CVDprocess includes Si—C covalent bonds while a silicon carbide materialformed using separate silicon precursors and carbon precursors does notinclude Si—C covalent bonds. Similarly, the silicon carbide materialformed by the radical CVD process includes Si—C covalent bonds, Si—Ocovalent bonds, and Si—N covalent bonds while a silicon carbide materialformed using separate silicon precursors, carbon precursors, nitrogenprecursors, and oxygen precursors does not include Si—C covalent bonds.

While embodiments herein describe the silicon carbide material as beingformed by the radical CVD process, an atomic layer deposition (ALD)process, such as a plasma enhanced ALD process, may alternatively beused. By way of example only, the silicon carbide material may be formedusing a plasma of Si₂Cl₆ and a plasma of CH₄ to form silicon carbide(SiC) or silicon carboxide (SiCO_(x)) following an O₂ plasma treatment.Silicon carboxynitride (SiCO_(x)N_(y)) may also be formed by ALD using asequential flow of Si₂Cl₆ and CH₃NH₂ plasma.

The conductive material 105E of the stacks 105 may be patterned to formconductive material 105E′, as shown in FIG. 3. The silicon carbidematerial of the liner 110B may be substantially resistant to a dry etchchemistry used to pattern the conductive material 105E after forming theliner 110A, 110B adjacent to (e.g., over) the stacks 105. However,portions of the liner 110 may be removed from the horizontal surfaces ofthe conductive material 105E and a portion of one or more of the liner110A, 110B may be removed from top portions of the stacks 105. Forinstance, a portion of the liner 110A, 110B adjacent to (e.g., over) atop surface of the stacks 105 and adjacent to (e.g., over) thehorizontal surfaces of the conductive material 105E may be removed,while a portion of the liner 110A, 110B remains on the sidewalls of thematerials 105A-105D of the stacks 105. The etch chemistry and etchconditions may, for example, remove the liner 110B from the top of thestacks 105, such as over the hardmask, while the liner 110A, 110Bremains on the sidewalls of the chalcogenide materials and/or theconductive carbon materials of the materials 105A-105E of the stacks105. The conductive material 105E may be etched by the same etchchemistry and etch conditions, forming the conductive material 105E′.While FIG. 2 shows the liner 110A, 110B as being substantiallycontinuous materials, the liner 110A, 110B may become discontinuousduring the patterning of the conductive material 105E, as shown in FIGS.3-7, due to the etch chemistry and etch conditions used.

The silicon carbide material of the liner 110B may also be substantiallyresistant to an aqueous hydrogen fluoride (HF) wet etch chemistry, suchas that used to remove residues (e.g., clean) the stack structures 100following the patterning of the conductive material 105E. The siliconcarbide material of the liner 110B may also be substantially resistantto hydrogen peroxide, citric acid, or ammonium hydroxide wet etchchemistries.

The liner 110B may be subjected to one or more treatment acts thatchange (e.g., reduce) the carbon content of the liner 110B, whichchanges (e.g., decreases) the dielectric constant of the liner 110Bcompared to the dielectric constant of the liner 110B as initiallyformed. After the treatment act, the liner 110B is referred to as thetreated liner 110B′ and is illustrated in FIG. 4 and subsequent drawingsas liner 110B′, indicating that the treatment act has been conducted.The dielectric constant of the silicon carbide material of the liner110B may be lower than the dielectric constant (about 8) of siliconnitride. The lower dielectric constant of the silicon carbide materialaccording to embodiments of the disclosure may enable the electronicdevice containing the silicon carbide material to mitigate high spikecurrent due to the high capacitance of the silicon carbide material. Thetreatment act may also densify the liner 110B, increasing the densityfrom about 1.8 g/cm³ to about 2.0 g/cm³. The treatment act may beconducted to tailor the carbon content of the treated liner 110B′ and toprovide the desired properties of the treated liner 110B′. The treatmentact may include exposing the liner 110B to an oxygen gas (O₂) treatmentact, such as an O₂ plasma treatment act. Without being bound by anytheory, it is believed that oxygen atoms in the oxidizing environment ofthe oxygen plasma treatment react with the carbon in the silicon carbidematerial to form carbon dioxide, which is volatile. A portion of thecarbon of the silicon carbide material may, therefore, be removed fromthe silicon carbide material following the oxygen plasma treatment act.The silicon carbide material of the treated liner 110B′, therefore,includes less carbon than the carbon content of the initially formedsilicon carbide material. To provide the desired etch selectivity duringsubsequent process acts, the silicon carbide material may contain atleast a minimal amount of carbon following the oxygen plasma treatmentact.

Process conditions, such as temperature, pressure, RF power, etc., ofthe oxygen treatment act may be chosen depending on the desired carboncontent in the treated liner 110B′. The process conditions may beconventional. The treatment act (e.g., the oxygen treatment) may beconducted after forming the silicon carbide material of the liner 110Bto a total desired thickness. Alternatively, the oxygen treatment may beconducted after forming an initial portion of the silicon carbidematerial, followed by forming one or more additional portions of thesilicon carbide material, followed by additional oxygen treatment acts.To prevent damage to the silicon carbide material, the oxygen treatmentmay be initially conducted at a low oxidation rate, followed byincreasing the oxidation rate after the silicon carbide material isformed to a sufficient thickness. Conducting multiple oxygen treatmentacts may increase the density of the liner 110B compared to conducting asingle oxygen treatment act. By way of example only, the density of theliner 110B may be increased from about 1.8 g/cm³-1.9 g/cm³ to about 2.0g/cm³ by doubling the number of oxygen treatment acts. The treated liner110B′ may include between about 2 at. % and about 50 at. % carbondepending on the treatment conditions used. If, for example, theformation of each silicon carbide material portion is followed by anoxygen plasma treatment, the silicon carbide material may includebetween about 2 at. % and about 5 at. % carbon. Conversely, if thesilicon carbide material is formed to the total desired thickness,followed by single plasma oxygen treatment, the silicon carbide materialmay include more carbon, such as from about 15 at. % to about 50 at. %carbon.

The silicon carbide material of the treated liner 110B′ differs from asilicon carbide material formed using separate silicon precursors andcarbon precursors as the source of silicon and carbon, respectively, andexposed to a similar treatment act. The treated silicon carbide materialformed by the radical CVD process includes Si—C covalent bonds while atreated silicon carbide material formed using separate siliconprecursors and carbon precursors does not include Si—C covalent bonds.

The treatment act may include nitrogen gas (N₂), ammonia (NH₃), orhydrogen gas (H₂) in addition to the oxygen gas. The treatment act mayalso include a carrier gas (e.g., inert gas), such as helium. Sinceoxygen gas is used during the treatment act and is incorporated into thesilicon carbide material, the silicon carbide material including oxygenmay, nevertheless, be formed even if the silicon-carbon precursor didnot include oxygen atoms. In other words, the source of oxygen in thesilicon carbide material including oxygen may be from the oxygen gasused in the treatment act. Similarly, if the treatment act includesnitrogen gas, the source of nitrogen in the silicon carbide materialincluding nitrogen may be from the nitrogen gas used in the treatmentact. The treatment act may include nitrogen gas (N₂), ammonia (NH₃), orhydrogen gas (H₂) in addition to the oxygen gas.

As shown in FIG. 4, a fill material 140 may be formed in the openings115. The distance D2 of the openings 115 may be sufficient for the fillmaterial 140 to be formed in the openings 115 without forming voids inthe fill material 140. The fill material 140 may, for example, be anelectrically insulative material, such as a dielectric material. Thefill material 140 may be a partially sacrificial material in that thefill material 140 is subsequently partially removed prior to completionof the electronic device that includes the stack structure 100. The fillmaterial 140 may, for example, be partially removed prior to completionof a first deck of the electronic device. Alternatively, the fillmaterial 140 may be present in the electronic device that includes thestack structure 100. The fill material 140 may, for example, be silicondioxide, silicon nitride, silicon oxynitride, silicon oxycarbide, aspin-on dielectric material (SOD), BPSG, BSG, an air gap, or anotherdielectric material. The silicon carbide material according toembodiments of the disclosure may also be used as the fill material 140such that the silicon carbide material substantially completely fillsthe openings 115. In some embodiments, the fill material 140 is aspin-on silicon dioxide. In other embodiments, the fill material 140 isa high quality, silicon dioxide. However, other fill materials 140 maybe used, such as by forming an air gap between the adjacent stacks 105.

The fill material 140 may substantially completely fill the openings115, as shown in FIG. 4. Excess fill material 140 over the stacks 105may subsequently be removed, such as by chemical mechanicalplanarization (CMP). A portion of the liner 110 may also be removed,such as from upper surfaces of the stacks 105, exposing the hardmaskmaterial or an electrode material of the stacks 105, as shown by thedashed line in FIG. 4. However, the liner 110 remains on the sidewallsof the stacks 105. If the fill material 140 is a dielectric material,the dielectric material may isolate memory cells of the electronicdevice from one another and may also provide mechanical support duringsubsequent process acts to form the electronic device including thesilicon carbide material.

The silicon carbide material according to embodiments of the disclosuremay also be used as a seal 125 in the stack structure 100, as shown inFIG. 5. The seal 125 may be formed adjacent to (e.g., over) the liner110 of the stack structure 100. The silicon carbide material of the seal125 may exhibit the same chemical composition or a different chemicalcomposition as the silicon carbide material of the liner 110B. The seal125 may substantially encapsulate the materials of the stacks 105 andremaining portions of the liner 110A, 110B. The silicon carbide materialof the seal 125 may be selected to be selectively etchable relative to aconductive material subsequently formed over the stacks 105, a portionof which is removed by a later process act to form, for example, a bitline. The seal 125 may substantially surround (e.g., encapsulate) thestacks 105 and the liners 110A, 110B, such as over top surfaces andsidewalls thereof. The seal 125 may be present on three surfaces of thestacks 105, providing a hermetic barrier that prevents water frompassing through the seal 125 and into the stacks 105. The seal 125 maydirectly contact the liner 110B, or may directly contact the stacks 105if no liner 110A, 110B is present. Subsequent drawings illustrate theseal 125 in direct contact with the liner 110B. However, the seal 125may directly contact the stacks 105 if a liner 110 is not present in thestack structure 100. While the seal 125 is illustrated in FIG. 5 asbeing a single material, the seal 125 may include multiple materials,such as a silicon nitride material and the silicon carbide material,with the silicon carbide material formed adjacent to (e.g., over) aninitial portion of the seal 125 (e.g., the silicon nitride material).

The seal 125 according to embodiments of the disclosure may be formed bysubstantially the same radical CVD process described above for the liner110B. However, the seal 125 may include the same amount of carbon, lesscarbon, or more carbon than the silicon carbide material of the liner110B. The silicon carbon precursor and the hydrogen radicals may besufficiently reactive with one another that plasma conditions are notused to form the seal 125. To form the seal 125, the stack structure 100including the stacks 105 and liners 110A, 110B, if present, may beplaced into a conventional reaction chamber and the silicon carbonprecursor and the hydrogen radicals introduced into the reaction chamberas described above. The silicon carbide material of the seal 125 may beformed until the desired thickness of the seal 125 is achieved.

The seal 125 may be formed at a sufficient thickness to protect thematerials 105A-105D of the stacks 105 and the liners 110A, 110B fromsubsequent process acts, which may oxidize or otherwise damage thematerials of the stacks 105 if the materials were to remain exposedduring the subsequent process acts. The thickness of the seal 125 issufficient to provide barrier properties without forming so-called“bottlenecks,” “pinch offs,” or “bread-loafing” between adjacent stacks105. The seal 125 may also provide protection during use and operationof the electronic device containing the seal 125, such as when hightemperatures and electrical fields may be present. For instance, thecarbon and/or chalcogenide materials of the stacks 105 may becomeoxidized or otherwise damaged when exposed to water or to processconditions used to form the stacks 105 or the liners 110A, 110B, such asduring patterning of the conductive material 105E. The seal 125 may beformed at a minimum thickness sufficient to provide the desired barrierproperties without forming bottlenecks or bread loafing around upperportions of the stacks 105 when the fill material 140 (see FIG. 6) isformed between the stacks 105. The thickness of the seal 125 may rangefrom about 10 Å to about 266 Å. The silicon carbide material of the seal125 may also be used as the fill material 140 by substantiallycompletely filling the openings 115′.

The seal 125 may be conformally formed over the liner 110B and may forma substantially continuous material over sidewalls and the upper portionof the stacks 105. The seal 125 may be substantially free of pinholes orother discontinuities. The seal 125 may be formed in the openings 115,which are defined by the sidewalls of the liner 110B or by the sidewallsof the stacks 105 if no liner 110 is present. The seal 125 may be formedon (e.g., adjacent to) the stacks 105 or the liner 110B, reducing thesize of the openings 115 to the openings 115′. After forming the seal125, the stacks 105 are separated from one another by a distance D3,which is less than the distances D1 and D2. The distance D3 may besufficient for the fill material 140 (see FIG. 6) to be formed in theopenings 115′ without voids forming in the fill material 140. The seal125 may exhibit a high degree of conformality and a high degree ofthickness uniformity (e.g., a high step coverage), reducing oreliminating bottlenecks and so-called “bread loafing” between the stacks105. Since sufficient space remains between the stacks 105 after formingthe seal 125, substantially no bottlenecks or bread loafing occur at orbetween the upper portions of the stacks 105. The seal 125 may exhibit aconformality of at least about 95%, such as greater than about 98% orgreater than about 99%. The thickness coverage (e.g., a ratio of thethickness of the seal 125 on the sidewalls to the thickness of the seal125 on the upper portions) of the seal 125 may be about 1:1.

The silicon carbide material of the seal 125 may be selected dependingon an etch rate selectivity of the seal 125 compared to other exposedmaterials of the stack structure 100, such as the hardmask material oranother conductive material, during later process acts. The carboncontent of the seal 125 may be selected to exhibit a substantiallysimilar etch rate to the other exposed materials to be removed duringlater process acts. The seal 125 is selected so that a portion of theseal 125 may be removed at a relatively fast etch rate with a high etchselectivity than other exposed materials. By increasing or decreasingthe carbon content of the seal 125, the etch rate and etch rateselectivity of the seal 125 may be tailored. By way of example only, fora given dry etch chemistry and/or process conditions, the seal 125 maybe etched at a faster etch rate if the silicon carbide material includesa higher amount of carbon than if the silicon carbide material includesa lower amount of carbon. For instance, the seal 125 and the hardmaskmaterial may exhibit similar etch rates and etch rate selectivities sothat the seal 125 and the hardmask material may be removed substantiallysimultaneously during subsequent process acts. The silicon carbidematerial of the seal 125 may also provide etch resistance to a wet etchchemistry and/or process conditions used to clean the stack structures100 before conducting subsequent process acts. For example, the siliconcarbide material of the seal 125 may be substantially resistant to anaqueous hydrogen fluoride (HF) wet etch chemistry, such as that used toclean the stack structure 100.

The fill material 140 may be formed in the openings 115′ between theadjacent stacks 105, as shown in FIG. 6. The fill material 140 may, forexample, be an electrically insulative material, such as a dielectricmaterial. The fill material 140 may be a partially sacrificial materialin that the fill material 140 is subsequently partially removed prior tocompletion of the electronic device that includes the stack structure100. The fill material 140 may, for example, be partially removed priorto completion of a first deck of the electronic device. Alternatively,the fill material 140 may be present in the electronic device thatincludes the stack structure 100. The fill material 140 may, forexample, be silicon dioxide, silicon nitride, silicon oxynitride,silicon oxycarbide, a spin-on dielectric material (SOD), BPSG, BSG, anair gap, or another dielectric material. The silicon carbide materialaccording to embodiments of the disclosure may also be used as the fillmaterial 140 such that the silicon carbide material substantiallycompletely fills the openings 115′. In some embodiments, the fillmaterial 140 is a spin-on silicon dioxide. In other embodiments, thefill material 140 is a high quality, silicon dioxide. Since the seal 125according to embodiments of the disclosure does not produce bottlenecksor bread loafing, the fill material 140 may substantially completelyfill the openings 115′, as shown in FIG. 6. The openings 115′ may besubstantially completely filled without forming voids in the fillmaterial 140. Excess fill material 140 over the stacks 105 maysubsequently be removed, such as by chemical mechanical planarization(CMP). A portion of the seal 125 and an optional cap 135 may also beremoved from upper surfaces of the stacks 105, exposing the hardmaskmaterial or an electrode material of the stacks 105, as shown by thedashed line in FIG. 6. However, the seal 125 and the cap 135 remain onthe sidewalls of the stacks 105. If the fill material 140 is adielectric material, the dielectric material may isolate memory cells ofthe electronic device from one another and may also provide mechanicalsupport during subsequent process acts to form the electronic device.

The stack structure 100 may also include the optional cap 135 on anupper surface of the seal 125, as shown in FIG. 6. The cap 135 may beformed on the seal 125 in situ or ex situ. A thickness of the cap 135relative to the thickness of the seal 125 is exaggerated in FIG. 6 forillustration purposes. The cap 135 may provide improved interfaceproperties between the seal 125 and the subsequently formed fillmaterial 140, enabling the fill material 140 to be formed in theopenings 115′ without forming voids. The cap 135 may, for example, be ahigh quality silicon oxide material. The cap 135 may be formed over theseal 125 by an ALD process, such as a conventional ALD process. The cap135 may be highly conformal and exhibit a high degree of thicknessuniformity.

The silicon carbide material of the seal 125 according to embodiments ofthe disclosure provides barrier properties to the stack structure 100,enabling the seal 125 to be formed without causing bread-loafing betweenadjacent stacks 105. Since less aggressive process conditions are usedto form the seal 125, the formation of the seal 125 according toembodiments of the disclosure does not damage or otherwise affectmaterials of the stack 105, such as the chalcogenide material or carbonmaterial, even when the seal 125 is formed directly on the materials ofthe stacks 105. Therefore, loss of the chalcogenide material may besubstantially reduced or eliminated compared to the chalcogenide lossobserved with conventional seal materials.

The stack structures 100 including the stacks 105, the silicon carbidematerial of the liner 110B and/or the seal 125, and the fill material140 may be subjected to conventional, additional process acts to formthe electronic device including the stack structures 100. By using thesilicon carbide material of the liner 110B, the conductive material 105Emay be selectively etched when exposed to a dry etch chemistry topattern the conductive material 105E. In addition, the etch resistanceof the silicon carbide material of the liner 110B and/or the seal 125may be increased when exposed to a wet etch chemistry used to removeresidues from the stack structures 100 before conducting additionalprocess acts. The stack structures 100 including the stacks 105, thesilicon carbide material of the liner 110B and/or the silicon carbidematerial of the seal 125 may also provide decreased parasiticcapacitance to the electronic device including the stack structures 100.

Since the liner 110 and or the seal 125 includes the silicon carbidematerial instead of a conventional silicon oxide material, the siliconcarbide material according to embodiments of the disclosure may provideone or more of etch selectivity, etch resistance, barrier properties, orchalcogenide loss to the electronic device containing the siliconcarbide material. By forming the liner 110 and or the seal 125 includingthe silicon carbide material, loss of sensitive materials (e.g.,chalcogenide materials, carbon materials) in the stacks is reduced. Theliner 110 and or the seal 125 over the materials of the stack 105 mayreduce redepositing of materials of the stack 105, which undesirablycauses leakage. By including carbon in the silicon carbide material, thesilicon carbide material provides etch selectivity relative to otherexposed materials of the electronic device during fabrication of theelectronic device. The etch selectivity of the silicon carbide materialmay be intermediate between that of silicon oxide and that of a high kdielectric material (from about 19 to about 20), such as aluminum oxideor hafnium oxide. As known in the art, using aluminum oxide or hafniumcauses high spike current due to high capacitance. Using the siliconcarbide material according to embodiments of the disclosure may decreaseissues associated with high spike current and high capacitance. Thesilicon carbide material according to embodiments of the disclosure isselectively etchable by dry etch chemistries used to form thanelectronic device containing the silicon carbide material compared toconventional silicon oxide liner materials. The silicon carbide materialaccording to embodiments of the disclosure is also more resistant to wetetch chemistries used to form than electronic device containing thesilicon carbide material than conventional silicon oxide linermaterials.

During subsequent process acts, the hardmask material of the stacks 105may be removed by conventional techniques and another conductivematerial (e.g., electrically conductive material) formed over theremaining materials of the stacks 105. The another conductive materialmay be patterned by conventional techniques to form, for example, a bitline (e.g., a digit line) or contact over the stack structure 100. Theanother conductive material may directly contact the conductive materialof the stacks 105, such as a conductive material configured as anelectrode of the stacks 105. As shown in FIG. 8 and described below, theanother conductive material may be configured as a bit line 806 (e.g., adigit line) of the electronic device that includes the stack structure100. An array 800 may include multiple memory cells 804 arranged in rowsand columns and that include the stack structure 100, with each memorycell 804 isolated (e.g., electrically isolated) from other memory cell804 by the liner 110 and/or the seal 125 and the fill material 140 ofthe stack structure 100. The memory cells 804 including the stackstructure 100 are positioned between access lines 802 (e.g., word lines)and bit lines 806 (e.g., digit lines).

Accordingly, an electronic device that comprises a stack structurecomprising one or more stacks of materials and one or more siliconcarbide materials is disclosed. The materials of the one or more stackscomprise a single chalcogenide material and one or more of a conductivecarbon material, a conductive material, and a hardmask material. The oneor more silicon carbide materials are adjacent to the one or more stacksof materials and comprise silicon carbide, silicon carboxide, siliconcarbonitride, silicon carboxynitride, or silicon boronitrocarbide. Theone or more silicon carbide materials also comprise silicon-carboncovalent bonds and the one or more silicon carbide materials areconfigured as a liner or as a seal.

Accordingly, a method of forming an electronic device is disclosed. Themethod comprises forming stacks of materials comprising one or morematerials, the one or more materials of the stacks comprising achalcogenide material. A silicon carbide material is formed by radicalchemical vapor deposition and is adjacent to the stacks of materials. Afill material is formed adjacent to the silicon carbide material andbetween adjacent stacks of the stacks of materials. The fill material issubstantially free of voids.

Accordingly, a method of forming an electronic device is disclosed. Themethod comprises forming stacks of materials comprising a chalcogenidematerial and one or more additional materials. Adjacent stacks of thestacks of materials are spaced apart by openings. A first siliconcarbide material is conformally formed by radical chemical vapordeposition and is adjacent to the stacks of materials. A portion of thefirst silicon carbide material adjacent to a conductive material of thestacks of materials is removed and an exposed portion of the conductivematerial is removed through the openings. A second silicon carbidematerial is conformally formed by radical chemical vapor deposition. Thesecond silicon carbide material is adjacent to the first silicon carbidematerial and in the openings. A fill material is formed between theadjacent stacks of the materials, the fill material substantially freeof voids.

Additional processing acts may be conducted to form the electronicdevice 900 that includes the array 800 of memory cells 804, whichinclude the stack structure 100 according to embodiments of thedisclosure, as shown in FIG. 9. The subsequent process acts areconducted by conventional techniques, which are not described in detailherein. The memory cells 804 including the stack structure 100 arepositioned between the access lines 802 (e.g., word lines) and the bitlines 806 (e.g., digit lines). The access lines 802 may be in electricalcontact with, for example, the conductive material 105E (e.g., tungsten)of the stacks 105 or an electrode (e.g., a bottom electrode), and thebit lines 806 may be in electrical contact with another electrode (e.g.,a top electrode) of the stacks 105. The bit lines 806 may directlyoverlie a row or column of the memory cells 804 including the stackstructure 100 and contact the top electrode thereof. Each of the accesslines 802 may extend in a first direction and may connect a row of thememory cells 804 (e.g., phase change memory cells). Each of the bitlines 806 may extend in a second direction that is at leastsubstantially perpendicular to the first direction and may connect acolumn of the memory cells 804. A voltage applied to the access lines802 and the bit lines 806 may be controlled such that an electric fieldmay be selectively applied at an intersection of at least one accessline 802 and at least one bit line 806, enabling the memory cells 804including the stack structure 100 according to embodiments of thedisclosure to be selectively operated. The electronic device 900including the array 800 of memory cells 804 may include memory cells 804containing one or more stacks of materials in which one or more of thematerials is sensitive to oxidation, heat, etc. As discussed above, thesensitive material may include a chalcogenide material, a carbonmaterial, etc. By way of example only, the electronic device may be a 3Delectronic device, such as a 3D crosspoint memory device, a PCRAM memorydevice, or other memory device including one or more materials sensitiveto oxidation and/or heat. The silicon carbide material according toembodiments of the disclosure may also be used in other electronicdevices where protection of sensitive materials is desired, such as in aDRAM memory device.

Accordingly, an electronic device that comprises an array of memorycells is disclosed. The memory cells comprise stacks of materialscomprising a chalcogenide material and one or more additional materials.One or more of the silicon carbide materials is adjacent to the stacksof materials, the one or more silicon carbide materials comprisingsilicon atoms and carbon atoms and the one or more silicon carbidematerials comprising silicon-carbon covalent bonds.

An electronic device 900 (e.g., a PCRAM memory device) according toembodiments of the disclosure is shown schematically in the functionalblock diagram of FIG. 9. The electronic device 900 may include at leastone memory cell 804 between at least one bit line 806 and at least onesource line 922. The memory cell 804 may be substantially similar to thememory cell 804 described above with reference to FIG. 8. The memorycell 804 may be coupled to an access device 910. The access device 910may act as a switch for enabling and disabling current flow through thememory cell 804. By way of non-limiting example, the access device 910may be a transistor (e.g., a field-effect transistor, a bipolar junctiontransistor, etc.) with a gate connected to an access line, for example,the access line 802. The access line 802 may extend in a directionsubstantially perpendicular to that of the bit line 806. The bit line806 and the source line 922 may be connected to logic for programmingand reading the memory cell 804. A control multiplexer 930 may have anoutput connected to the bit line 806. The control multiplexer 930 may becontrolled by a control logic line 932 to select between a first inputconnected to a pulse generator 926, and a second input connection toread-sensing logic 928.

During a programming operation, a voltage greater than a thresholdvoltage of the access device 910 may be applied to the access line 802to turn on the access device 910. Turning on the access device 910completes a circuit between the source line 922 and the bit line 806 byway of the memory cell 804. After turning on the access device 910, abias generator 929 may establish, by way of the pulse generator 926, abias voltage potential difference between the bit line 806 and thesource line 922. During a read operation, the bias generator 929 mayestablish, by way of the read-sensing logic 928, a read bias voltagepotential difference between the bit line 806 and the source line 922.The read bias voltage may be lower than the reset bias voltage. The readbias voltage enables current to flow through the memory cell 804. Forexample, for a given read bias voltage, if the chalcogenide material ofthe stacks 105 is in a high-resistance state (e.g., a reset state), arelatively smaller current flows through the memory cell 804 than if thechalcogenide material of the stacks 105 is in a low-resistance state(e.g., a set state). The amount of current flowing through the memorycell 804 during the read operation may be compared to a reference inputby the read-sensing logic 928 (e.g., a sense amplifier) to discriminatewhether the data stored in the memory cell 804 is a logic “1” or a logic“0.” In some embodiments, the source line 922 may coincide with theaccess line 802 and the access device 910 may not be present. The pulsegenerator 926 and read-sensing logic 920 may bias the access line 802 ata voltage sufficient for the memory cell 804 to self-select.

A system 1000 is also disclosed, as shown in FIG. 10, and includes theone or more memory cells 804 according to embodiments of the disclosure.FIG. 10 is a simplified block diagram of the system 1000 implementedaccording to one or more embodiments described herein. The system 1000may comprise, for example, a computer or computer hardware component, aserver or other networking hardware component, a cellular telephone, adigital camera, a personal digital assistant (PDA), portable media(e.g., music) player, a Wi-Fi or cellular-enabled tablet such as, forexample, an iPad® or SURFACE® tablet, an electronic book, a navigationdevice, etc. The system 1000 includes at least one electronic device900, which includes memory cells 804 including the stack structures 100as previously described. The system 1000 may further include at leastone processor 1002, such as a microprocessor, to control the processingof system functions and requests in the system 1000. The processor 1002and other subcomponents of the system 1000 may include memory cells 804according to embodiments of the disclosure. The processor 1002 may,optionally, include one or more electronic devices 900 as previouslydescribed.

The system 1000 may include a power supply 1004 in operablecommunication with the processor 1002. For example, if the system 1000is a portable system, the power supply 1004 may include one or more of afuel cell, a power scavenging device, permanent batteries, replaceablebatteries, and rechargeable batteries. The power supply 1004 may alsoinclude an AC adapter. Therefore, the system 1000 may be plugged into awall outlet, for example. The power supply 1004 may also include a DCadapter such that the system 1000 may be plugged into a vehiclecigarette lighter or a vehicle power port, for example.

Various other devices may be coupled to the processor 1002 depending onthe functions that the system 1000 performs. For example, an inputdevice 1006 may be coupled to the processor 1002. The input device 1006may include input devices such as buttons, switches, a keyboard, a lightpen, a mouse, a digitizer and stylus, a touch screen, a voicerecognition system, a microphone, or a combination thereof. A display1008 may also be coupled to the processor 1002. The display 1008 mayinclude an LCD display, an SED display, a CRT display, a DLP display, aplasma display, an OLED display, an LED display, a three-dimensionalprojection, an audio display, or a combination thereof. Furthermore, anRF sub-system/baseband processor 1010 may also be coupled to theprocessor 1002. The RF sub-system/baseband processor 1010 may include anantenna that is coupled to an RF receiver and to an RF transmitter (notshown). A communication port 1012, or more than one communication port1012, may also be coupled to the processor 1002. The communication port1012 may be adapted to be coupled to one or more peripheral devices1014, such as a modem, a printer, a computer, a scanner, or a camera, orto a network, such as a local area network, remote area network,intranet, or the Internet, for example.

The processor 1002 may control the system 1000 by implementing softwareprograms stored in the memory. The software programs may include anoperating system, database software, drafting software, word processingsoftware, media editing software, or media playing software, forexample. The memory is operably coupled to the processor 1002 to storeand facilitate execution of various programs. For example, the processor1002 may be coupled to system memory 1016, which may include phasechange random access memory (PCRAM) and other known memory types. Thesystem memory 1016 may include volatile memory, non-volatile memory, ora combination thereof. The system memory 1016 is typically large so thatit can store dynamically loaded applications and data. In someembodiments, the system memory 1016 may include electronic devices, suchas the electronic device 900 of FIG. 9, and memory cells, such as thememory cell 804 described above with reference to FIG. 8.

The processor 1002 may also be coupled to non-volatile memory 1018,which is not to suggest that system memory 1016 is necessarily volatile.The non-volatile memory 1018 may include PCRAM to be used in conjunctionwith the system memory 1016. The size of the non-volatile memory 1018 istypically selected to be just large enough to store any necessaryoperating system, application programs, and fixed data. Additionally,the non-volatile memory 1018 may include a high capacity memory such asdisk drive memory, such as a hybrid-drive including resistive memory orother types of non-volatile solid-state memory, for example. Thenon-volatile memory 1018 may include electronic devices, such as theelectronic device 900 of FIG. 9, and memory cells, such as the memorycell 804 described above with reference to FIG. 8.

Accordingly, a system comprising an input device, an output device, anda processor operably coupled to the input device and output device isdisclosed. An electronic device is operably coupled to the processor andcomprises memory cells that comprise stacks of materials comprising asingle chalcogenide material and one or more additional materials. Atleast one silicon carbide material is vertically adjacent to the stacksof materials and on sidewalls of the single chalcogenide material. Athickness of the at least one silicon carbide material is substantiallyuniform along a length thereof.

The following examples serve to explain embodiments of the disclosure inmore detail. These examples are not to be construed as being exhaustiveor exclusive as to the scope of this disclosure.

EXAMPLES Example 1

Ten samples of silicon carboxide materials exhibiting different carboncontents were formed by varying the amount of silicon-carbon precursorused to form the silicon carbide material and the amount of O₂ used inthe plasma treatment act. The silicon carboxide materials were formed onblanket wafers. A ratio of the amount of silicon-carbon precursor to theamount of O₂ is shown in Table 1. The silicon-carbon precursor was aliquid precursor, octamethyl-cyclotetrasiloxane (C₈H₂₄O₄Si₄, molar mass296.62, vapor pressure: about 124.5 Pa+/− about 6.2 Pa at 25° C.), andwas commercially available from Sigma-Aldrich Corps (St. Louis, Mo.).The number of O₂ plasma treatment cycles (e.g., single and/or multipledeposition and treatment cycles) was also varied to determine the effecton the carbon content of the silicon carboxide materials.

TABLE 1 Conditions Used To Form Silicon Carboxide Materials Ratio ofNumber of O₂ silicon-carbon plasma treatment Bulk Carbon Bulk Si/OSample precursor to O₂ cycles (at. %) (at. %) 1 2.28 X cycles 16.038.7/45.2 2 4.00 X cycles 21.2 38.9/39.9 3 8.00 X cycles 25.6 39.3/35.14 7.00 X cycles 24.4 39.7/35.9 5 6.00 X cycles 23.7 39.6/36.7 6 2.28 2Xcycles 15.6 39.3/45.0 7 4.00 2X cycles 20.1 40.0/39.0 8 8.00 2X cycles25.0 40.3/34.7 9 7.00 2X cycles 24.0 40.5/35.4 10 6.00 2X cycles 22.940.8/36.3

The remote hydrogen plasma was generated away from the surface of thewafers at an RF power ranging from about 200 W to about 2 kW. A remoteplasma design with a so-called “downstream plasma” configuration using aFaraday Grid to filter out unwanted ions electrons, and unwanted UVradiation was used. The remote plasma design enabled only the desiredfree radicals and neutral species (e.g., the hydrogen radicals) to reactwith the silicon-carbon precursor to form the reaction product. Theliquid silicon-carbon precursor was supplied from a bulk cabinet andintroduced to a chamber containing the blanket wafers at a flow rategreater than or equal to about 50 ml/minute at a pressure of greaterthan or equal to about 20 psig (+/− about 10 psig), with additional pushpressure imparted to the liquid delivery flow from inside the bulkcabinet. The introduction of the liquid silicon-carbon precursoroccurred near or above the surface of the blanket wafers. Subsequentactivation of the silicon-carbon precursor with hydrogen radicals,radical reactions, and O₂ plasma treatment produced silicon carboxidefilms.

As shown in FIG. 11, silicon carbide materials including between 15 at.% and 26 at. % carbon were formed. The oxygen content of the siliconcarbide materials is shown in FIG. 12, and ranged between about 34 at. %and 45 at. %.

Example 2

Wet etch rates in aqueous HF solutions of varying concentrations of oneof the silicon carboxide materials of Example 1 were measured byconventional techniques. The silicon carboxide materials were formed onblanket wafers. The aqueous HF solutions included 200:1 HF, 100:1 HF,and 10:1 HF. As shown in FIGS. 13A-13D, substantially no etch (about 0Å/min) of the silicon carbide material was observed, even with the mostconcentrated aqueous HF solution.

Example 3

Density, leakage density, and dielectric constants of the siliconcarboxide materials (Samples 1-10 in Example 1) were calculated ormeasured by conventional techniques and are shown in Table 2. Thesilicon carboxide materials were formed on blanket wafers.

TABLE 2 Properties of Silicon Carboxide Materials Leakage density Bulkdensity at 3 MV/cm Dielectric Sample (g/cm³) (A/cm²) constant 1 1.9 Nodata k ≤ 4.5 2 1.8 4.62 × 10⁻⁸ k ≤ 4.5 3 1.8 No data k ≤ 4.5 4 1.9 Nodata k ≤ 4.5 5 1.9 4.83 × 10⁻⁹ k ≤ 4.5 6 2.0 2.00 × 10⁻⁸ k ≤ 4.5 7 2.08.30 × 10⁻⁸ k ≤ 4.5 8 2.0 1.36 × 10⁻⁸ k ≤ 4.5 9 2.0 5.50 × 10⁻⁹ k ≤ 4.510 2.0 6.51 × 10⁻⁹ k ≤ 4.5

As shown in Table 2, increasing the number of O₂ plasma treatment cyclesincreased the density of the silicon carboxide materials. The samplesexposed to X number of cycles had a density between about 1.8 g/cm³ and1.9 g/cm³, while the samples exposed to 2× number of cycles had adensity of about 2.0 g/cm³. The dielectric constants of the siliconcarboxide materials were lower than the dielectric constant (about 8) ofsilicon nitride.

Example 4

The extent of chalcogenide loss caused by forming the silicon carboxidematerials over stacks including the chalcogenide material was determinedby conventional techniques. The silicon carboxide materials were formedon sidewalls of the stacks. The stacks including the chalcogenidematerial were similar to the stacks illustrated schematically in FIG. 1and were high aspect ratio stacks. The silicon carboxide materialsincluded 5 at. % carbon, 13 at. % carbon, 14 at. % carbon, or 15 at. %carbon. As shown in FIG. 14, the percentage of germanium loss wascomparable for forming the silicon carboxide material over the stackmaterials, forming the treated silicon carboxide material over the stackmaterials, and forming a conventional silicon oxide material over thestack materials. As shown in FIG. 15, the percentage of indium loss wasless for forming the silicon carboxide material over the stack materialsand forming the treated silicon carboxide material over the stackmaterials compared to forming a conventional silicon oxide material overthe stack materials.

While certain illustrative embodiments have been described in connectionwith the figures, those of ordinary skill in the art will recognize andappreciate that embodiments encompassed by the disclosure are notlimited to those embodiments explicitly shown and described herein.Rather, many additions, deletions, and modifications to the embodimentsdescribed herein may be made without departing from the scope ofembodiments encompassed by the disclosure, such as those hereinafterclaimed, including legal equivalents. In addition, features from onedisclosed embodiment may be combined with features of another disclosedembodiment while still being encompassed within the scope of thedisclosure.

What is claimed is:
 1. An electronic device comprising: a stackstructure comprising one or more stacks of materials, the materials ofthe one or more stacks comprising a single chalcogenide material and oneor more of a conductive carbon material, a conductive material, and ahardmask material; and one or more silicon carbide materials adjacent tothe one or more stacks of materials, the one or more silicon carbidematerials comprising silicon carboxide, silicon carbonitride, siliconcarboxynitride, or silicon boronitrocarbide, the one or more siliconcarbide materials comprising silicon-carbon covalent bonds, and the oneor more silicon carbide materials configured as a liner or as a seal. 2.The electronic device of claim 1, wherein a first silicon carbidematerial of the one or more silicon carbide materials directly contactsa liner material adjacent to the stacks of materials.
 3. The electronicdevice of claim 1, wherein a first silicon carbide material of the oneor more silicon carbide materials directly contacts sidewalls of thestacks of materials.
 4. The electronic device of claim 1, wherein asecond silicon carbide material of the one or more silicon carbidematerials directly contacts the first silicon carbide material.
 5. Theelectronic device of claim 1, wherein a second silicon carbide materialof the one or more silicon carbide materials directly contacts a sealmaterial adjacent to the stacks of materials.
 6. The electronic deviceof claim 1, wherein the one or more silicon carbide materials comprisesa carbon content of from about 2 atomic percent (at. %) to about 50 at.% carbon.
 7. The electronic device of claim 1, wherein the one or moresilicon carbide materials comprises a homogeneous chemical composition.8. The electronic device of claim 1, wherein the one or more siliconcarbide materials comprises a gradient of carbon across a thickness ofthe one or more silicon carbide materials.
 9. The electronic device ofclaim 1, wherein a chemical composition of the one or more siliconcarbide materials configured as a liner comprises a different chemicalcomposition as the one or more silicon carbide materials configured as aseal.
 10. The electronic device of claim 1, wherein a chemicalcomposition of the one or more silicon carbide materials configured as aliner comprises the same chemical composition as the one or more siliconcarbide materials configured as a seal.
 11. The electronic device ofclaim 1, wherein adjacent stacks are spaced at a half pitch of fromabout 10 nm to about 30 nm.
 12. The electronic device of claim 1,further comprising a fill material in direct contact with the one ormore silicon carbide materials.
 13. The electronic device of claim 12,wherein the till material comprises an additional portion of the one ormore silicon carbide materials.
 14. An electronic device comprising: anarray of memory cells, the memory cells comprising: stacks of materialscomprising a chalcogenide material and one or more additional materials;and one or more silicon carbide materials adjacent to the stacks ofmaterials, the one or more silicon carbide materials comprising siliconatoms, carbon atoms, and atoms of at least one other chemical element,and the one or more silicon carbide materials comprising silicon-carboncovalent bonds; and access lines and bit lines electrically coupled tothe memory cells.
 15. The electronic device of claim 14, wherein thestacks of materials comprise an aspect ratio of from about 10:1 to about50:1.
 16. The electronic device of claim 14, wherein the stacks ofmaterials comprise a single chalcogenide material.
 17. The electronicdevice of claim 1, wherein the chalcogenide material comprises indium.18. The electronic device of claim 1, wherein the chalcogenide materialcomprises germanium.
 19. The electronic device of claim 14, wherein thestacks of materials comprise a single chalcogenide material.